- XCENA unveiled its MX1 Computational Memory with thousands of RISC-V cores at FMS 2025.
- The chip supports near-data processing, reducing CPU-memory bottlenecks.
- Roadmap includes MX1P in 2025 and MX1S in 2026, both leveraging CXL 3.2.
- MX1 won “Most Innovative Memory Technology” at FMS 2025 and comes with an SDK for developers.
At the Future of Memory and Storage (FMS 2025), a small but ambitious South Korean startup decided to steal the spotlight. The company, XCENA, pulled the curtain back on its very first product, the MX1 Computational Memory, and the crowd paid attention.
The reason? MX1 is not just another chip, it is stuffed with thousands of RISC-V cores and designed to move compute right next to memory. For decades, computing has been bogged down by the endless game of ping-pong between CPUs and DRAM. XCENA thinks it has found a way to stop wasting time on that back-and-forth.
This new approach, called near-data processing, could end up rewriting the rulebook on how servers are designed in the years to come.
So Many Cores, You’ll Lose Count
Let’s start with the flashy number: thousands. XCENA says the MX1 is packed with in-house designed RISC-V cores, not just for bragging rights, but for a purpose. These cores sit right next to DRAM and take over workloads that are usually memory-hungry nightmares: things like vector database queries, analytics tasks, and AI inference.
By crunching data where it lives instead of forcing it to travel to a faraway CPU, the MX1 saves time and energy. Anyone who has ever watched a server farm sweating under massive AI loads will understand the appeal.
The chip is built on PCIe Gen6 and the Compute Express Link (CXL) 3.2 standard, giving it modern connectivity and the flexibility to slip into next-gen server designs. Think of it as moving the kitchen right next to the dining table—you cut down on the wait and stop wasting energy running back and forth.
Goodbye Bottlenecks, Hello Petabytes
One of the biggest headaches in computing is the bottleneck between memory and processing. CPUs are fast, DRAM is fast, but the trip between them is often painfully slow. XCENA’s pitch is simple: keep processing as close as possible to memory and skip the wasted motion.
The MX1 is not only about speed; it also brings scalability. Thanks to SSD-backed memory expansion, the chip supports petabyte-scale capacity. Imagine servers with seemingly bottomless memory pools, complete with compression and reliability features baked in.
For data centers drowning in AI and analytics workloads, the promise of high throughput combined with vast memory expansion is like dangling a lifeline.
The Roadmap: Patience Required, Excitement Guaranteed
XCENA is not just dropping one chip and walking away. It has a roadmap that shows how serious it is about this new category of hardware.
- The MX1P will arrive later this year, with working samples scheduled for select partners starting in October 2025.
- The MX1S is planned for 2026 and will feature dual PCIe Gen6 x8 links plus some added horsepower.
Both products will lean on the full capabilities of CXL 3.2, which gives developers more bandwidth and more flexibility to integrate them into diverse server environments.
In short, this is not a one-off science project. XCENA is betting that computational memory is a trend about to explode, and it wants to lead the charge.
Awards, Applause and a Pat on the Back
Recognition came quickly. At FMS 2025, the MX1 walked away with the “Most Innovative Memory Technology” award. That is no small feat, considering how crowded and competitive the memory and storage market has become.
It also marks the second year in a row that XCENA has impressed at the event. In 2024, it was crowned “Most Innovative Startup”, which makes this back-to-back win something worth bragging about.
Industry voices are echoing the hype. Jay Kramer, Chair of the Awards Program and President of Network Storage Advisors, praised computational memory as a breakthrough that reduces data movement and boosts efficiency for data-intensive workloads.
In his words, MX1 is the first computational memory controller to support CXL 3.X, which is exactly why it is attracting so much attention.
Developers, You’re Invited to the Party
Launching impressive hardware is one thing. Getting developers to actually use it is another. XCENA knows this, which is why it is rolling out a software development kit (SDK) alongside the MX1.
The SDK includes drivers, runtime libraries, and tools to help teams test, evaluate, and deploy MX1 into real-world environments. Importantly, the stack is designed to fit into standard software ecosystems, so developers do not have to reinvent the wheel just to get started.
XCENA’s message is clear: whether you are building AI inference pipelines, running in-memory analytics, or experimenting with new data-heavy workloads, the MX1 should slot in without breaking your existing workflows.
A Startup With Big Ambitions
XCENA may be new—it was founded in 2022 under the name MetisX, but it is already making a case for being a company to watch. In just a few years, it has gone from a fresh face to a back-to-back award winner with a product that could shake up the way servers are built.
The timing could not be better. Data centers are under enormous strain from AI training, analytics, and large-scale data processing. Traditional architectures are showing their limits, and the market is hungry for a rethink.
If XCENA’s MX1 delivers what it promises, it could be one of the first real-world examples of how near-data processing goes from concept to cornerstone of modern computing.
The company is not pretending that MX1 will solve every problem overnight. But by putting compute and memory in the same neighborhood, it might just be lighting the path for the next generation of server design.
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